Substrates that include one or more semiconductor materials are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (for example, logic processors and memory devices), radiation emitting devices (for example, light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity surface emitting lasers (VCSELs)), radiation sensing devices (for example, optical sensors) and electronic devices utilized in power control systems. Such semiconductor devices are conventionally formed in a layer-by-layer manner (lithographically) on and/or in a surface of a semiconductor substrate.
Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in) or more). Although silicon wafers generally have thicknesses of several hundred microns (for example, about 700 microns) or more, only a very thin layer (for example, less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is actually used to form active devices on the silicon wafer.
It has been discovered that the operational speed and power efficiency of semiconductor devices can be improved by electrically insulating the portion of the semiconductor material on a semiconductor substrate that is actually used to form the semiconductor devices from the remaining bulk semiconductor material of the substrate. As a result, so-called “engineered substrates” have been developed that include a relatively thin semiconductor material (for example, a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a dielectric material (for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3)). Optionally, the dielectric material may be relatively thin (for example, too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the dielectric material may be disposed on a relatively larger host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment. The base substrate is often referred to in the art as a “handle” or “handling” substrate.
A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), III-V type semiconductor materials, and II-VI type semiconductor materials.
For example, an engineered substrate may include an epitaxial III-V type semiconductor material formed on a surface of a base substrate, such as aluminum oxide (Al2O3) (which may be referred to as “sapphire”). Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial III-V type semiconductor material to form one or more devices on the engineered substrate.
Due to a natural tendency of atoms of different material layers to align with one another, when a semiconductor material is formed (for example, epitaxially grown) over another material (for example, a different underlying semiconductor material), the atoms of the crystal layer tend to “strain” (i.e., stretch or compress) to align with the atoms of the lattice of the underlying material. The formation and use of strained layers of semiconductor material is limited because these strained layers may develop detrimental defects, such as dislocations, due to mismatch of the lattice parameters between adjacent materials. Depending on its particular composition, the semiconductor material may be grown only to a particular thickness, often referred to as a “critical thickness,” before defects and separation of compositional phases begin to develop. The critical thickness of a material is dependent on a number of parameters, including for example, the lattice structure of the underlying material, the composition of the semiconductor material, and the growth conditions under which the semiconductor material is formed. Dislocations may form above a critical thickness when a lattice parameter mismatch exists between the semiconductor material and the underlying substrate material. When forming these layers epitaxially, both a high doping concentration and increased material thickness may be desirable to reduce electrical resistivity. However, as the concentration of dopant and the thickness of the semiconductor material are increased, preserving a crystal structure having low defect density may become increasingly difficult.
For example, indium gallium nitride (InxGa1-xN) devices may be formed on an engineered substrate by growing one or more epitaxial device layers each comprising indium gallium nitride on a gallium nitride (or indium gallium nitride) seed layer formed on the engineered substrate. Mismatch in the crystal lattice structures of the adjacent layers of indium gallium nitride may induce strain within the crystal lattice of one or more of the layers, which may effectively limit the thickness of the layers and/or the concentration of indium therein. Lattice strain is more problematic (e.g., in terms of obtaining good device performance) in indium gallium nitride device layers having higher indium content and increased thicknesses.
The presence of such lattice strain in a semiconductor material may be undesirable for a number of reasons. For example, the presence of lattice strain in a semiconductor material may result in an increased density of defects (e.g., lattice dislocations) in the semiconductor material, undesirable morphology at the surface of the semiconductor material, and may even result in the formation of cracks in the semiconductor material. Furthermore, the presence of lattice strain in a semiconductor material may facilitate the onset of undesirable separation of material phases within the semiconductor material.
Forming an indium gallium nitride seed layer on the surface of an engineered substrate in such a manner that the indium gallium nitride seed layer has a lattice parameter that will match that of an indium gallium nitride device layer to be formed thereover may be difficult to reach. As a result, the crystal lattice of the overlying indium gallium nitride device layer may be strained upon formation thereof when using the underlying indium gallium nitride seed.
Borophosphosilicate glass (BPSG) may be used as a compliant material to produce relaxed indium gallium nitride. For example, the indium gallium nitride may be formed over the BPSG (e.g., by a bonding process) and a viscosity (or fluidity) of the BPSG may be decreased to relax the strain of the overlying indium gallium nitride. In fabricating BPSG, a viscosity of the BPSG varies with a concentration of boron and/or phosphorous therein. For example, a temperature at which the BPSG begins to flow may be reduced by increasing the concentration of boron in the BPSG. Accordingly, the concentration of boron and/or phosphorus in BPSG may be controlled so that the BPSG flows by the proper amount at a desired temperature.
In order to determine the concentration of boron and/or phosphorus in the BPSG, a reference sample is conventionally tested with a measuring instrument utilizing X-rays or infrared rays during fabrication of indium gallium nitride device layers. However, the concentration of boron and/or phosphorus may change over time as these impurities react with water or other atmospheric compounds. As a result, it may be difficult to determine and maintain a desired concentration of boron and/or phosphorus and, thus, a consistent flow rate of BPSG during fabrication of indium gallium nitride device layers over BPSG material. In addition, the BPSG material may be an electrical insulator and therefore may substantially prevent the flow of electrons across the BPSG material. The use of such insulating BPSG materials may therefore prevent vertical current flow through engineered substrates comprising BPSG materials and thereby may limit the design and optimization of device structures formed on such engineered substrates.